library verilog;
use verilog.vl_types.all;
entity keyboard is
    port(
        clk             : in     vl_logic;
        key_R           : in     vl_logic_vector(3 downto 0);
        key_C           : out    vl_logic_vector(3 downto 0);
        codeout         : out    vl_logic_vector(7 downto 0)
    );
end keyboard;
